The present disclosure relates to a semiconductor memory device and, more particularly, to a word line block select circuit.
Generally, when the parameter of tRCD (Row Address to Column Address Delay) is measured, a considerable delay is caused to decide whether to activate a redundancy word line or a normal word line while an active command is input and a word line is activated.
Therefore, many difficulties arise from a time loss and several variables due to a delay tuning for improvement of the tRCD. Accordingly, a processing margin is required for a stable operation in a semiconductor memory device and this margin leads to a tRCD loss.
FIG. 1 is a diagram of a conventional word line block select circuit 100.
As shown in FIG. 1, the conventional word line block select circuit outputs a word line block select signal bs using an active command signal act and a repair control signal repair_sum from a repair address decision unit. That is, the word line block select signal bs is utilized to decide whether to activate a redundancy word line or a normal word line.
Here, the redundancy word line is connected to a dummy cell which is substituted for a bad cell in a memory core. The repair address decision unit decides whether an address signal corresponds to the bad cell or a normal cell.
In FIG. 1, a delay chain 101 is provided for compensating for the time required in the repair address decision unit. Since the time delayed in the repair address decision unit changes according to many variables, the delay chain 101 has an additional delay chain, such as a metal option, in order to compensate for the time delay caused by the variables.
In FIG. 1, in case that a redundancy word line is to be activated by performing a logic operation using both a delayed active signal act_d, which is delayed for time compensation in the delay chain 101, and the repair control signal repair_sum from the repair address decision unit, a logic operation unit 102 outputs the word line block select signal bs which can block a signal path for activating the normal word line and select the redundancy word line.
However, the conventional word line block select circuit has a problem in that the delay chain 101 is formed on the path for activating the normal word line in order to compensate for the time delay caused by the several variables and a processing margin of more than a few nanoseconds is taken.
Also, it is required to correct the metal option in case that the redundancy word line and the normal word line are activated simultaneously due to the lack of the margin. That is, the conventional block select circuit has problems of a tRCD deterioration caused by the margin which is required for a stable operation, and a time loss caused by the metal option correction.